Static memory cells do not require a refresh operation, so they have low power dissipation as compared with dynamic random access memories (DRAMs). The refresh operation is an operation of charging and discharging the capacitance of a DRAM for storing a "0" or "1" as bit information. Such an operation is needed because the capacitance of the DRAM always leaks the stored electric charges from the junction portions, insulating films, and depletion layers.
FIG. 1 shows the structure of a DRAM. Data is stored in a capacitance 1, the structure of which is shown in FIG. 2. That is, an insulating film 3 is interposed between electrodes 2. Since the miniaturization of memories has recently been required, the distance d between the electrodes 2 has to be made smaller. If the distance is made smaller, the thickness of the insulating film 3 will be reduced and the leakage current i between the electrodes will increase. Such an increase in the leakage current means that a refresh operation must be more frequently performed. Therefore, as memories are made smaller, the DRAM has the disadvantage that its refresh operation becomes complicated.
As described above, static memory cells do not require a refresh operation. This is due to the structure and operating principle of a static memory cell such as that shown in FIG. 3. The operating principle is as follows: two inverter circuits are cross coupled. For example, if a CL terminal is at a high electric potential, and since a CLB terminal goes to a low electric potential such as ground, transistors TN.sub.1 and TP.sub.2 will be turned on, transistors TN.sub.2 and TP.sub.1 will be turned off. As a result, the voltage on the CL terminal is maintained high, so this state is stored as information. Since in such a static memory cell this state is maintained by a feedback latch, information will not be lost as long as power is not switched off. Therefore, a refresh operation such as a DRAM is not needed and an additional circuit such as a control clock also becomes unnecessary.
However, even though static memory cell has the abovedescribed advantages, it has the disadvantage that the area occupied by the circuit is large. That is, a feedback circuit for maintaining the voltage levels of circuit terminals is required and a large number of elements for that circuit need to be used, so the chip area is increased. More specifically, while a DRAM is constituted by one capacitor and one transistor for selection, a static memory needs four transistors for a feedback circuit and two transistors for selection as long as it uses a CMOS circuit and therefore the area of a cell is very large. This disadvantage is critical in these days when the miniaturization of elements is desired.
A device element called a quantumdevice has been developed in recent years. The quantum device is one which uses the quantum-mechanical property of free electrons to perform information processing. Many of the quantum devices heretofore developed have an I-V characteristic such as the one shown in FIG. 4. By using the negative differential resistance of this quantum device (characteristic that I is reduced as V is increased), a positive feedback circuit can be constituted with a simpler structure such as that shown in FIG. 5.
The relationship between FIGS. 4 and 5 will hereinafter be described. FIG. 5 illustrates an example of a simple positive feedback using a quantum device, in which a quantum device 8 is connected in series to a resistor 7. The voltage on this connection point A can be represented by (V.sub.o -iR), when the voltage on a point B on the side of the resistor 7 opposite to the quantum device 8 is V.sub.b. If the relationship between this voltage and current i is expressed in FIG. 4, it will become a straight line 6. This straight line is generally called a load line. In FIG. 4, the abscissa represents a voltage V and the ordinate represents a current i, and the point of intersection between the load line 6 and the abscissa is V.sub.o. On the other hand, the voltage-current behavior of the quantum device 8 is shown by a curve 9 in FIG. 4. While the points of intersection P.sub.1, P.sub.2, and P.sub.3 between the load line 6 and the curve 9 have been shown, the current i flowing through a resistor is aligned with the voltage-current behavior of the quantum device at the voltages and currents indicated by the points, and the positive feedback circuit shown in FIG. 5 is stabilized as one system.
That is, if two of (i.sub.1, V.sub.1) according to the point P.sub.1 of FIG. 4 and (i.sub.3, V.sub.3) according to the point P.sub.3 are considered, a system becomes stable at these two voltage-current conditions and exhibits a positive feedback circuit characteristic. Therefore, the point A of FIG. 5 can express a bit 0 or 1 in correspondence with the voltages V.sub.1, V.sub.3 according to these two points.
Since a positive feedback circuit using the conventional quantum device described above is stabilized at certain voltages V.sub.1 and V.sub.3, currents i.sub.1 and i.sub.3 corresponding to the voltages always flow in the stabilized state. A current that thus flows constantly in a stable state is called a standby current. If heat is generated by the standby current, there will be an important disadvantage that the degree of integration of a circuit is limited. That is, the memory cell using the conventional quantum device has the disadvantage of a standby current, because the circuit is not complementary.
To cope with the problems as produced by the prior art, the present invention proposes quite a new method of storing information and a new structure of a static memory.
It is an object of the present invention to provide a memory cell which is structurally simpler than memories being presently used.
It is another object of the present invention to provide a memory cell which has positive feedback.
Another object of the present invention is to provide a memory cell which has an area equivalent to the cell area of a DRAM and dispenses with a refresh operation.
Still another object of the present invention is to form a memory cell with a quantum device.
A further object of the present invention is to constitute the circuit complementarily and to greatly reduce the standby current.